The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structures.
In the past, the semiconductor industry utilized various techniques to produce transistors that have a low on-resistance and a high breakdown voltage. One particular technique utilized a plurality of P and N type strips arranged on a P-type semiconductor substrate. One example of such a structure is disclosed in U.S. Pat. No. 6,097,063 entitled xe2x80x9cSemiconductor Device Having A Plurality of Parallel Drift Regionsxe2x80x9d issued to Tatsuhiko Fujihira on Aug. 1, 2000. When such a device was connected as a high side driver, latch-up often occurred and the transistor was damaged or destroyed. Another problem was that the on-resistance often changed after the device was manufactured. Further, to obtain a usable on-resistance, the stripes had to be deep and narrow resulting in increased manufacturing costs. Typically, the depth was greater than two microns while the width was greater than one-half micron. Such an aspect ratio made the device difficult to manufacture.
Accordingly, it is desirable to have a transistor with a low on-resistance, that can also be connected as a high side driver and that does not latch-up or damage the transistor, that has reduced manufacturing costs, and that has an on-resistance that does not drift after manufacturing.